1. Field of the Invention
The present invention relates to a charge pump circuit, particularly relates to a charge pump circuit having switching circuits for reducing leakage current used for Phase-locked loop (PLL) circuit.
2. Description of the Related Art
A PLL circuit is widely used to regenerate a clock for example in a field of a communication and others.
FIG. 6 shows the general configuration of a PLL circuit using a charge pump circuit. The PLL circuit 101 shown in FIG. 6 roughly includes a phase-frequency comparator 102, an inverter 103, a charge pump circuit 104, a lowpass filter (LPF) 105, a voltage controlled oscillator (VCO) 106 and a frequency divider 107.
The PLL circuit divides the frequency of an internal clock output from VCO 106 via the frequency divider 107 and compares the phase with that of a reference clock from an external device in the phase-frequency comparator 102. When the phase of the reference clock is faster than that of the output of the frequency divider (the frequency of the internal clock is smaller than a reference value), the frequency of output from VCO is increased by applying a positive signal to VCO 106, when the phase of the reference clock is slower than that of output from the frequency divider (the frequency of the internal clock is more than the reference value), feedback operation is executed by applying a negative signal to VCO 106 so that the frequency of output from VCO is reduced and the frequency of the internal clock from VCO 106 is always synchronized with that of a reference clock.
At this time, the charge pump circuit 104 supplies charging current to LPF 105 according to an up* signal (* shows an inverted signal) acquired by inverting an up (UP) signal output from the phase-frequency comparator 102 via the inverter 103 when the phase of a reference clock is faster than that of the output of the frequency divider and when the phase of a reference clock is slower than that of the output of the frequency divider, discharge current is generated from LPF 105 via the charge pump circuit 104 according to a down signal output from the phase-frequency comparator 102. LPF 105 functions as a lowpass filter by integrating according to a time constant CR determined based upon a value R of resistance 105A and a value C of capacity 105B and stabilizes the operation of the PLL circuit 101 by smoothing the output of the charge pump circuit 104.
FIG. 7 shows an example of the configuration that a P-channel transistor 1, a P-channel transistor 2, an N-channel transistor 3 and an N-channel transistor 4 are sequentially connected in series between a power source VDD and a ground GND of the charge pump circuit. The source of the P-channel transistor 1 is connected to a power source VDD and is operated as a constant current source by applying bias voltage VBP lower than power supply voltage VDD to the gate. The P-channel transistor 2 is turned on when an up* (UP*) signal sent to the gate is at a low level (the potential of GND), supplies constant current from the power source VDD via the P-channel transistor 1 to LPF 105 and is turned off when an up* signal is at a high level (the potential of VDD). The source of the N-channel transistor 4 is connected to GND and the transistor functions as a constant current source by applying bias voltage VBN higher than the potential of GND to the gate. The N-channel transistor 3 is turned on when a down (DN) signal sent to the gate is at a high level, constant current flows to GND from LPF 105 via the N-channel transistor 4 and the N-channel transistor 3 is turned off when a down signal is at a low level.
As described above, the charge pump circuit 104 controls the frequency of a clock output from VCO 106 by combining a constant current source and a switching circuit and supplying charging/discharge current to LPF 105 according to an up signal or a down signal.
Recently, the reduction of voltage to be applied to a CMOS transistor composing a circuit from an operating power source is desired as an integrated circuit is miniaturized. However, generally when operating power supply voltage to a CMOS transistor is reduced, the threshold voltage (Vth) lowers and hereby, leakage current increases when a CMOS transistor is turned off.
A PLL circuit shown in FIG. 6 also has a problem that when each transistor in the charge pump circuit shown in FIG. 7 is turned off, leakage current increases because of the reduction of voltage.
That is, in a phase locked state that the feedback control of a PLL circuit is constricted and no up signal and no down signal are generated by the phase-frequency comparator, the P-channel transistors 1 and 2 and the N-channel transistors 3 and 4 in the charge pump circuit are all turned off. However, in this state, as LPF 105 is charged in case leakage current flows out of the P-channel transistors 1 and 2 and the N-channel transistors 3 and 4, input potential to VCO 106 varies and the frequency of an output clock also varies in a state in which a phase is to be locked. The variation described above of the frequency changes depending upon the degree of leakage current in the P-channel transistors 1 and 2 and the N-channel transistors 3 and 4, for example the frequency of an output clock is offset or jitter occurs in the frequency of an output clock.
The present invention is made in view of the above situation and the object is to provide a PLL circuit wherein the offset of the frequency of an output clock and the occurrence of jitter in the frequency respectively caused by leakage current in a transistor composing a charge pump circuit can be prevented in the PLL circuit operated at low voltage.
To achieve the object, a first aspect of the invention relates to a charge pump circuit comprising:
a first current source transistor;
a first switching circuit electrically connecting a source electrode of said first current source transistor to a first voltage source when said first switching circuit receives a first control signal whereby said first current source transistor supplies a charge current from said first voltage source to an output terminal, and electrically connecting said source electrode of said first current source transistor to a second voltage source when said first switching circuit receives a second control signal whereby said first current source transistor is cut from said charge current;
a second current source transistor; and
a second switching circuit electrically connecting a source electrode of said second current source transistor to a third voltage source when said second switching circuit receives a third control signal whereby said second current source transistor discharges a discharge current from said output terminal to said third voltage source, and electrically connecting said source electrode of said second current source transistor to a fourth voltage source when said second switching circuit receives a fourth control signal whereby said second current source transistor is cut off.
In the configuration according to the invention, as the PLL circuit provided with the charge pump circuit is activated or inactivated according to an up signal or a down signal generated when the phase of a clock output from the voltage controlled oscillator is faster or slower than the phase of a reference clock for generating current for charging or discharging the lowpass filter for controlling the frequency of a clock output from the voltage controlled oscillator according to the output of the lowpass filter. The charge pump circuit is composed of a first current source transistor for instructing the charge pump circuit to charge the lowpass filter, a first switching transistor for connecting the source of the first current source transistor to a power source according to an up signal, a second current source transistor for discharging the lowpass filter and a second switching transistor for grounding the second current source transistor according to a down signal and bias is applied to the first or second current source transistor when the charge pump circuit is not activated, leakage current from the current source transistor in the charge pump circuit can be reduced and therefore, offset and jitter can be prevented from occurring in the frequency of a clock output from the voltage controlled oscillator because of leakage current described above.